Automation Inc. Targets Creation of
Statistical Timing Models
Santa Clara, California -- July 3, 2006 - Altos Design Automation Inc. has been formed to develop and market new cell characterization technology and tools for IC designers who are working on complex SoCs (system-on-chip) designs at 90nm, 65nm and 45nm process technologies, with emphasis on the creation of statistical timing models.
The Altos solutions - the first of which is being introduced today - run at least an order of magnitude faster than the current generation of in-house and/or commercial cell characterization tools and bring fully-automated vector generation capabilities to IC designers to alleviate the arduous manual setup requirements of many current tools.
Altos, which is privately funded, was founded in January 2005 by former CadMOS alumni, including Jim McCanny, the Altos Chief Executive Officer; Ken Tseng, Chief Technology Officer and Kevin Chou, Vice President of Research and Development. The founders moved to Cadence when that company bought CadMOS in 2001. At Cadence, the team was involved in developing timing and signal integrity analysis technology. For complete biographies, go to: http://www.altos-da.com/team.html
"Characterization is at the cornerstone of the design flow, enabling every step from RTL synthesis through to electrical signoff." Said McCanny, "Designers at 90nm and below need a lot more library views than before to manage leakage, signal integrity, dynamic power consumption and yield",
McCanny continued, "However because current characterization flows take too long, designs are often taped out with old or inappropriate PVT (process, voltage, temperature) corners. This results in slipped design schedules and a much higher risk of silicon failure. At 65nm and below, where statistical timing models are needed, the characterization bottleneck becomes even more acute."
"We believe statistical static timing analysis (SSTA) will be essential for high yields at 65nm and 45nm. However, creation of statistical timing models is potentially a major barrier to SSTA adoption. There is a huge increase in the number of simulations required to accurately model systematic and random process variation," said Tseng. "At Altos, we've been able to speed up characterization by over an order of magnitude for both nominal and statistical models, essentially removing this roadblock and paving the pathway between DFM/DFY flows and design implementation."
Altos deploys a novel "inside view" approach to characterization where each cell is pre-analyzed to create the optimal vector set and simulation conditions to maximize throughput and ensure full coverage of all logic states. In addition, Altos has integrated its own highly-tuned Spice engine to further reduce the simulation overhead, although 3rd party circuit simulators such as SpectreŽ, HspiceŽ or EldoŽ are also supported. Altos' "inside view" is especially effective for modeling the impact of random process variation where each transistor within a cell can vary independently.
Altos Design Automation provides ultra-fast, fully-automated characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization. Altos advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield.
Privately held, Altos was founded in 2005 in Santa Clara, CA. Its current corporate headquarters are at 4020 Moorpark Avenue, Suite 100, San Jose, CA 95117 Telephone: (408) 980-8056.