Altos Design Automation Inc. Releases Liberate, an Ultra-Fast, Fully Automated Library Characterizer
New Tool Supports
Current Source Models for Timing and Noise
Santa Clara, California -- July 3, 2006 - Altos Design Automation Inc. today announced its first product Liberate, a high-speed, fully automated library characterizer for standard cells and I/Os that supports the creation of advanced current source models for timing (CCS and ECSM) and signal integrity (CCSN). Liberate delivers a significant reduction in characterization costs and turnaround time coupled with improvements in ease of use and model quality.
Jim McCanny ,
Altos CEO and founder said, "Characterization has become increasingly
challenging due to both the increase in the number of views and the complexity
of the cells required to support low power, high yielding nanometer designs." McCanny
continued, "Liberate because of its fast performance and the quality
of its models enables designers to get all the views they need to fully validate
their design thereby reducing the risk of silicon failure".
Liberate’s Key Advantage
Liberate uses a novel "inside view" approach for characterization. Rather than the traditional black-box method, each circuit is pre-analyzed to determine the minimal required set of simulation vectors, the most optimal way to condition each simulation and initial bounds for constraint determination. By using automatic vector generation Liberate avoids potential errors caused by manual or pseudo-manual vector creation where certain logic states can be overlooked, increasing the risk of silicon failure. This is especially helpful for complex cells such as state retention flops that deploy power gating techniques and sleep modes to reduce power consumption.
"New models such as CCSN for signal integrity require a new approach to characterization." said Ken Tseng, Altos CTO and founder, "The black-box approach that is widely used by many existing tools is no longer effective. By performing upfront circuit analysis to understand the internals of each cell, characterization time can be dramatically reduced and improved models can be created”.
Once the correct stimulus for each circuit is determined the simulations can be performed either by Altos' highly-tuned built-in Spice engine or by a 3rd party circuit simulator such as Spectre®, Hspice® or Eldo®. Using the combination of Altos’ “inside view” circuit analysis and the integrated simulator results in an order of magnitude improvement in characterization turnaround time and a highly-accurate cell model where every logic state is accounted for.
In addition, to the traditional non-linear delay, power and signal integrity models, Liberate generates advanced current source timing models that are especially effective at modeling the impact of voltage (IR) drop on delay.
"Advanced current source timing models such as CCS and ECSM require careful selection of the sampling points." said Kevin Chou, Altos VP of Engineering and founder, "Select too many points and the library data size explodes, select too few and you lose accuracy. Liberate is able to capture the correct number of samples via on the fly validation and dynamically adjusting the sample range to minimize size while ensuring accuracy”.
Liberate is available now. Altos’ products are sold directly in North America and via a distributor, Marubeni Solutions Corp., in Japan.
Altos Design Automation provides ultra-fast, fully-automated characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization. Altos advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield.
Privately held, Altos was founded in 2005 in Santa Clara, CA. Its current corporate headquarters are at 4020 Moorpark Avenue, Suite 100, San Jose, CA 95117 Telephone: (408) 980-8056.