Altos’ Cell Characterization Tools Used for TSMC’s 40nm Libraries

 

Variety™ and Liberate™ characterize libraries for

the most advanced TSMC process


San Jose, California -- June 3rd 2008 - Altos Design Automation Inc. today announced their cell characterization tools are used for TSMC’s 40nm standard cell library development.  TSMC uses the Altos tools to characterize its 40G and 40LP low power libraries.  Specifically, TSMC uses Liberate to generate CCS (current composite source) and ECSM (effective current source model) views for timing, noise and power. Variety is used to create SSTA (statistical static timing analysis) models for multiple SSTA tools.

“TSMC is the first commercial foundry to offer a 40nm manufacturing technology process. Along with it, we provide library support as chip and power performance requirements are increasingly stringent”, said Cliff Hou, Director of TSMC Design Service Division.   “Altos’ characterization tool suite enhances our ability to accurately and quickly create all necessary views necessary to implement high-speed, low-power 40nm designs.”

 

 

“We see TSMC’s adoption of our cell characterization products for their internal use as a testimonial to Altos’ technology.  Rapid cell characterization plays a crucial role in enabling adoption of TSMC latest 40nm process technology,” said Jim McCanny, CEO of Altos.   “We look forward to assisting TSMC with their future library requirements and to enabling TSMC’s customers to enjoy the same advantages of using our ultra-fast characterization products.”

 

About Liberate

Liberate is an ultra fast library creator that generates electrical models in Liberty® format. Liberate supports all the latest models for timing, noise and power such as CCS (Composite Current Source) and ECSM (Effective Current Source Models). Liberate also supports low power design styles that include power gating cells, state retention registers and level shifters.

 

About Variety

Variety creates statistical timing cell models that represent the non-linear impact of any number of systematic and random parameter variations.  All library timing data is characterized for variation including delays, transitions, timing constraints and pin capacitances. Variety generates SSTA models for a number of commercial SSTA products from a single characterization run.