Altos Design Automation Inc. Announces Liberate™ LV a Comprehensive Library Validation Solution 



San Jose, California – July 15, 2009 – Altos Design Automation Inc. today announced Liberate LV, an independent and comprehensive solution to validate cell libraries. Using Liberate LV, library teams will be able to assure the quality of all the electrical views in the library. This includes checking all functional, timing, noise, and power data for potential problems before wide-spread use by multiple design teams.


Liberate LV performs a number of necessary library validation steps including ensuring functional consistency between the transistor level sub-circuits and the Liberty® , Verilog and Vital files; accuracy validation of electrical analysis tools analysis versus SPICE circuit simulation and library version comparison. The output from Liberate LV is either a report in text, Excel or HTML format or a graphical display of potential errors.


"Advanced libraries contain millions of data points that are captured and manipulated during library characterization." said Jim McCanny, Altos CEO, "Any error or unnecessary margin in any of these data points can lead to multiple chip failures, unnecessary design iterations and less competitive chips. It is necessary to qualify libraries coming from IP suppliers to ensure that the library works with your preferred tool suite, is up to date with your process models and is free from missing or bad data”.

The Liberate LV Edge

Typically library validation is performed in an ad-hoc manner with a different set of tools used to check different aspects of the library data. Liberate LV integrates all of these checks and more into a single validation system. It supports checking multiple electrical analysis tools, logic simulators and multiple “golden” SPICE simulators. It also has an API (ALAPI) to allow users to write their own additional checks.


The checks performed by Liberate LV belong to four distinct categories:

1)     Functional validation to ensure the function information represented by each cell’s extracted transistor level netlist is equivalent to the function information stored in the library and with the function description contained in the Verilog and Vital library views. In addition checks are made to ensure that all of the necessary logic states (“when” conditions) for each cell have been characterized completely. A missing state could mean over or under-estimation of worst-case timing and/or power.

2)     Data consistency checks to ensure that al the library data is within expected ranges and exhibits the expected trends, for example delay data should be monotonically increasing as the output loading increases. Liberate LV will also check that SDF data created from the library using a timing analysis tool will annotate correctly with a given logic simulator using the Verilog and/or Vital library views.

3)     Data comparison to previous versions of the library to identify unexpected changes when a new version of the library is received or created. Library data can change depending on the version of the process models, the cell layouts, the SPICE simulator, characterization software and/or characterization settings.

4)     Accuracy validation of the data within the library including timing, power and noise with and without current source models (CCS and/or ECSM). Each state of each arc of each cell requires checking with the appropriate analysis tools and the results compared against golden SPICE simulations.


Liberate LV supports validation of all cell types including sequential cells, tri-state buffers and complex gates. Cells can be validated as a chain complete with interconnect and additional fan out cells to create test circuits that can identify potential weakness in the selection of table indices. The accuracy analysis performed by Liberate LV can be fully distributed across a network of computers each with multiple CPUs. Platfrom Computing’s LSF, SUN’s Sungrid and Runtime Design Automation’s Flow Tracer are all supported for job distribution. Comparison of statistical timing analysis versus Monte Carlo simulation is also available in Liberate LV.


Liberate LV supports multiple electrical analysis tools including Synopsys PrimeTime® (SI, PX and VX), Cadence’s Encounter® Timing System (L, XL and GXL), Extreme DA’s GoldTimetm and Incentia’s TimeCraft®.  Synopsys Hspice® and VCS®, Cadence’s Spectre® and NC-Verilog® and Mentor’s Eldo® and ModelSim® are all supported for SPICE and logic simulation respectively.

Pricing and Availability


Liberate LV is available now, U.S. pricing starts at $75K for a one- year license. Altos’ products are sold directly in Europe and North America and via distributors in Japan, Taiwan and Korea.

About Altos
Altos Design Automation provides ultra-fast, fully-automated characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization.  Altos advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield. 

Privately held, Altos was founded in 2005 in Santa Clara, CA.  Its corporate headquarters is at 4020 Moorpark Ave., Suite 100, San Jose, CA 95117. Telephone: (408) 980-8056. On the Web at: