New “Dynamic Partitioning” dramatically reduces runtime, improves accuracy
Liberate MX extends Altos “inside view” technology with “automatic probing” and “dynamic partitioning” to address the run-time, accuracy challenges that come with characterizing large macro blocks with millions of transistors. By utilizing vectors and a “fast-spice” simulator, Liberate MX is able to identify critical paths that can be condensed into “dynamic partitions”. These “dynamic partitions” can be accurately characterized using the same methods as standard cells using a “true-spice” simulator. This results is a dramatic improvement in both run-time (often 10X or more for large memories) and accuracy. Large 1Mbit memory instances have been fully characterized in less than a few hours on a single machine.
Cathy Kao (Shu-Yi Kao), Design Methodology Manager of Realtek Semiconductor Corp. said, "We evaluated Liberate MX on many different memory types from multiple IP suppliers including SRAM, ROM, CAM, and register files. We found it to be very fast and easy to use. Using Liberate MX enables us to quickly create accurate memory models that are best tuned for use in our designs".
"At advanced process nodes its becoming imperative to characterize every unique on-chip memory instance." said Jim McCanny, Altos CEO, "Relying on the library models output from memory compilers is no longer sufficient due to excessive margins and inaccuracies caused by “fitting”. We developed Liberate MX to provide designers with an easy, automated and efficient way to create accurate models that match the needs of their target application. This enables designers to better manage their power budget and to close timing much sooner. Furthermore, Liberate MX’s intelligent utilization of simulation and compute resources will help design managers reduce their costs."
The Liberate MX Advantage
Unlike traditional block characterization approaches which perform partitioning based on circuit topology, Liberate MX’s use of “dynamic partitioning” is able to account for effects common at advanced process nodes such as interconnect coupling and transistor stress. As ‘dynamic partitions” are smaller they can be simulated faster and/or with higher accuracy without overwhelming the “true-spice” simulator. Liberate MX does not rely on circuit pattern matching and hence can be used for a very wide range of circuit types from complex lower power SRAMs with power gating to custom blocks such as SERDES.
In addition to current source timing and noise models, Liberate MX generates pin capacitance, state-dependent leakage and non-linear models for timing and power. Liberate MX can read input vectors or generate them from a high level truth table. The tool automatically identifies clock trees and latch nodes within the circuit to determine timing constraints reducing the onus on the engineer to manually specify measurement probes. The library models generated by Liberate MX are consistent with those created by Liberatetm for standard cells and I/Os which is essential for reliable electrical sign-off of System-on-Chip (SoC) designs.
Liberate MX supports multiple “fast-spice’ simulators including
Synopsys CustomSim (HSIM®, NanoSim®
Pricing and Availability
Liberate MX is available now,
Altos Design Automation provides ultra-fast, fully-automated characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization. Altos advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield.
Privately held, Altos was founded in 2005 in