NetLogic Microsystems Utilizes Altos’ Liberate MX for Embedded Memory Characterization on 40nm Tapeout

San Jose, California – May 10, 2010 - Altos Design Automation Inc. today announced that NetLogic Microsystems (Mountain View, CA) has adopted Liberate MX for instance-specific memory characterization. NetLogic Microsystems has successfully used the Altos product to characterize memory instances on its recent 40nm tapeouts.


Dimitrios Dimitrelis, Vice President of Engineering at NetLogic Microsystems, said, “Our advanced 40nm designs include a significant number of embedded memory blocks.  We have successfully used Liberate MX to create instance-specific models for memory arrays for our latest chip. Creating accurate memory models enabled us to meet our aggressive timing goals.”


Jim McCanny, Altos CEO and founder said, “Today’s SoCs have a significant amount of on-chip memory that contributes to the chip’s overall performance and power consumption. Designers can no longer rely on approximate models created from memory compilers but need to characterize each unique instance to get a highly accurate timing, power and noise models that are essential to ensure good silicon correlation.” McCanny continued, “Using Liberate MX, NetLogic Microsystems has been able to efficiently create models that are targeted to their low voltage application enabling them to meet their timing and power budgets and quickly get to working silicon.”


About Liberate MX

Unlike traditional memory characterization approaches which rely either entirely on “fast SPICE” simulation or  static cutting based on circuit topology, Liberate MX’s uses “dynamic partitioning” to reduce each memory instance into a smaller set of representative circuits. These compact “partitions” are suitable for characterization using a “true SPICE” simulator such as Eldo®, Hspice® or Spectre®. Consequently, Liberate MX is able to account for effects common at advanced process nodes such as interconnect coupling and transistor stress.  Liberate MX generates pin capacitance, state-dependent leakage and both non-linear and current source models for timing, noise and power. The tool automatically identifies clock trees and latch nodes within the circuit to determine timing constraints reducing the onus on the engineer to manually specify measurement probes. The library models generated by Liberate MX are consistent with those created by Liberatetm for standard cells and I/Os enabling reliable electrical optimization and sign-off of the complete chip.


Liberate MX supports multiple “fast-spice’ simulators including Synopsys CustomSim (HSIM®, NanoSim® and XA), Mentor’s ADiT and Cadence’s Virtuoso® UltraSim Full Chip Simulator that are used to perform its “dynamic partitioning” step.

About Altos
Altos Design Automation provides ultra-fast, fully-automated characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization.  Altos advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield. 

Privately held, Altos was founded in 2005 in Santa Clara, CA.  Its corporate headquarters are at 4020 Moorpark Ave., Suite 100, San Jose, CA 95117. Telephone: (408) 980-8056. On the Web at:

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